GLM-5.3 Flash on Chinese Silicon

Q: What the Model Actually Is

GLM-5.3 Flash is 320B total parameters, only 18B active per token. Released Aug 25 under MIT license. 190K HuggingFace downloads in five days. Here's what I found in the config:

Z.AI confirmed this week that GLM-5.3 Flash — their latest 320B-parameter MoE model — is running all inference on domestically manufactured Chinese hardware. I cloned the repo and read the config down to the last weight tensor. Then I traced what that hardware actually is, what it can and can't do, and whether the gap is closing or widening.

The short version: the model is genuinely impressive. The hardware story is more sobering than the headlines suggest.

What the Model Actually Is

GLM-5.3 Flash is 320B total parameters, only 18B active per token. Released Aug 25 under MIT license. 190K HuggingFace downloads in five days. Here's what I found in the config:

Architecture

45 transformer layers with a hybrid attention scheme:

graph TD
  A[Input Tokens] --> B{45 Layers}
  B -->|34 layers| C[Linear Attention
MLA-style, kv_lora_rank=512]
  B -->|11 layers| D[Sparse Attention
deepseek-style indexer
top-2048, 32 heads]
  C --> E[MoE FFN
288 experts, 8 active/token]
  D --> E
  E --> F[Manifold-Constrained
Hyper-Connections]
  F --> G[Next Layer]

34 linear attention layers (MLA-style with KV LoRA rank 512 — compresses KV cache to 512 dimensions instead of full hidden_size 4096)
11 deepseek_sparse_attention layers — indexer selects top-2048 keys from the KV pool using 32 index heads at 128 dim each, with key-pool compression and always-select-tail for streaming
288 routed experts (MoE intermediate=2048), 8 experts per token, 1 shared expert, noaux_tc top-k routing
MLP layers: first 3 are dense (intermediate_size=12288), remaining 42 are MoE-sparse. Only the first 3 layers have dense MLPs
mHC (Manifold-Constrained Hyper-Connections) with hc_mult=4 and 20 Sinkhorn iterations — a learned gating mechanism between attention and FFN outputs
1M max context (1,048,576 positions)
1 multi-token prediction (MTP) layer for speculative decoding
24-layer ViT vision encoder — 1024 hidden, 448px input, patch-size 14, temporal-patch-size 2 (video support), 10240-dim projection intermediate

Every layer gets its own hyper-connection learnable base and scale. The quantization config lists dozens of per-layer exceptions for FP8 — this model shipped with dynamic FP8 (e4m3) weight quantization out of the box.

What This Means

The architecture is a deliberate bet on inference efficiency over training simplicity. The hybrid attention (MLA for most layers, sparse indexer for the 11 where it matters) works because the linear attention handles the bulk of the sequence cheaply while the sparse layers handle retrieval. The 288-experts-8-active MoE with noaux_tc routing keeps the compute budget low. This is a model designed to run cheaply at scale, not to win the FLOP-measuring contest.

On the benchmarks they published: approaches Claude Opus 4.8 on coding and agentic tasks. NL2Repo, DeepSWE, Terminal-Bench, and Toolathlon all show competitive numbers. The reasoning_effort parameter (low/high/max) controls thinking budget.

The Hardware Story

Z.AI confirmed the model runs all inference on Chinese-manufactured chips. They didn't name the chipmaker or publish throughput numbers. Nobody has independently verified the claim.

Martin Alderson published a detailed analysis yesterday breaking down the plausible hardware. The key takeaways:

The current HiSilicon 910c series pairs 96GB HBM2e with ~1.6 PFLOP/s INT8 at 600W. That's ~60% of an H100 (a 4-year-old Nvidia part). No native FP8 support. The next-gen 950-series uses domestically produced HiZQ/HiBL HBM memory in two variants (950PR for prefill, 950DT for decode) — a workaround for restricted HBM supply.

The hard wall: EUV lithography. Without it, you can't fab below ~7nm. You hit a thermal ceiling. You can't produce fast HBM either. China is investing heavily in domestic EUV, but the most optimistic timelines put reliable volume production after 2030 — and ASML took 25 years to get there.

China's strategy: throw quantity at the problem. Build 10x as many slower chips for the same inference capacity. The math almost works for inference, but not for training. Power costs multiply. KV cache margin shrinks. Batch sizes stay small.

Where This Leaves Us

Three things are true simultaneously:

GLM-5.3 Flash is a genuinely good model — competitive architecture, MIT license, multimodal, 18B active. It's not a paper tiger. The architecture choices are smart and defensible.
China can run SOTA inference on domestic silicon — the 910c is good enough for production inference. The 950-series with domestic HBM proves the vertical integration is happening.
The gap is not closing for training — without EUV, thermal density caps compute per chip. Western chips keep pulling ahead (OpenAI's Jalapeño does 1.5-1.9x the work per watt of Nvidia's GB300). The inference gap may even widen as Western hardware moves to 2nm-class nodes.

The quantity-over-quality strategy works for inference because inference is embarrassingly parallelizable and power-constrained rather than latency-constrained. But it doesn't transfer to training — where fast interconnects, large contiguous memory, and single-die compute matter. China can serve GLM-5.3 Flash to users. Training the next generation of it still needs TSMC.

Bottom Line

GLM-5.3 Flash is proof that Chinese software and architecture engineering is world-class. The model design choices — hybrid attention, aggressive MoE sparsity, KV compression, FP8 quantization — are ahead of many Western labs' thinking. But the hardware it runs on is a generation behind, and the fabrication bottleneck is structural. China can serve inference. Training supremacy still belongs to whoever holds the EUV tools.